VHDL 4Bit 병렬 가감산기

LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITTY EX_3_2 IS
PORT(
 A, B, C, D : IN STD_LOGIC;
 LT, BI, RBI : IN STD_LOGIC;
 S_A, S_B, S_C S_D : OUT STD_LOGIC;
 S_E, S_F, S_G, RBO : OUT STD_LOGIC;
 COM : OUT STD_LOGIC_VECTOR(1 TO 6)
 );
END EX_3_2;

ARCHITECTURE HB OF EX_3_2 IS

 SIGNAL TMP_D : STD_LOGIC_VECTOR(3 DOWN TO 0);
 SIGNAL TMP : STD_LOGIC_VECTOR(6 DOWNTO 0);

BEGIN
 
 TMP_D < A & B & C & D;
 COM(1) <= '0';
 COM(2 TO 6)  <= "11111";
 
PROCESS( LT, RBI, BI, TMP)
BEGIN
 IF LT = '0' AND BI = '1' THEN
  TMP <="1000000";
  RBO <='1';
 ELSIF LT = '1' AND RBI = '0' AND TMP_D = "0000" THEN
  TMP <="1111111";
  RBO <='0';
 ELSIF BI = '0' THEN
  TMP <="1111111";
  RBO <='1';
 ELSIF LT = '1' AND RBI = '1' AND BI = '1' THEN
  TMP <= "111110";
  RBO <='1';
 ELSIF LT = '1' AND BI = '1' THEN
  CASE TMP_D IS
   WHEN "0001" = > TMP <="0110000";
    RBO<='1';
   WHEN "0010" = > TMP <="0110000";
    RBO<='1';
   WHEN "0011" = > TMP <="0110000";
    RBO<='1';
   WHEN "0100" = > TMP <="0110000";
    RBO<='1';
   WHEN "0101" = > TMP <="0110000";
    RBO<='1';
   WHEN "0110" = > TMP <="0110000";
    RBO<='1';
   WHEN "0111" = > TMP <="0110000";
    RBO<='1';
   WHEN "1000" = > TMP <="0110000";
    RBO<='1';
   WHEN "1001" = > TMP <="0110000";
    RBO<='1';
   WHEN OTHERS => NULL;
  END CASE;
 NED IF;
END PROCESS;

S_A <= TMP(6);
S_B <= TMP(5);
S_C <= TMP(4);
S_D <= TMP(3);
S_E <= TMP(2);
S_F <= TMP(1);
S_G <= TMP(0);

END HB;