VHDL 4Bit 병렬 가감산기
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITTY EX_3_2 IS PORT( A, B, C, D : IN STD_LOGIC; LT, BI, RBI : IN STD_LOGIC; S_A, S_B, S_C S_D : OUT STD_LOGIC; S_E, S_F, S_G, RBO : OUT STD_LOGIC; COM : OUT STD_LOGIC_VECTOR(1 TO 6) ); END EX_3_2; ARCHITECTURE HB OF EX_3_2 IS SIGNAL TMP_D : STD_LOGIC_VECTOR(3 DOWN TO 0); SIGNAL TMP : STD_LOGIC_VECTOR(6 DOWNTO 0); BEGI..
2009. 5. 21.
